US 11,714,924 B2
Unified addressable memory
Manu Gulati, Saratoga, CA (US); Joseph Sokol, Jr., San Jose, CA (US); Jeffrey R. Wilcox, San Jose, CA (US); Bernard J. Semeria, Palo Alto, CA (US); and Michael J. Smith, San Francisco, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 8, 2021, as Appl. No. 17/469,591.
Application 17/469,591 is a continuation of application No. 16/859,634, filed on Apr. 27, 2020, granted, now 11,138,346.
Application 16/859,634 is a continuation of application No. 15/748,893, granted, now 10,671,762, issued on Jun. 2, 2020, previously published as PCT/US2016/048697, filed on Aug. 25, 2016.
Claims priority of provisional application 62/234,275, filed on Sep. 29, 2015.
Prior Publication US 2022/0058292 A1, Feb. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/72 (2013.01); G06F 12/02 (2006.01); G06F 12/1027 (2016.01); G06F 12/14 (2006.01); G06F 21/78 (2013.01); H04L 9/08 (2006.01)
CPC G06F 21/72 (2013.01) [G06F 12/0246 (2013.01); G06F 12/1027 (2013.01); G06F 12/1408 (2013.01); G06F 21/78 (2013.01); H04L 9/0861 (2013.01); H04L 9/0894 (2013.01); G06F 2212/7206 (2013.01); G06F 2212/7208 (2013.01); G06F 2221/2143 (2013.01); H04L 2209/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a non-volatile memory, wherein at least a portion of the non-volatile memory is addressable as main memory, and wherein data in the main memory is non-persistent with a power down of the system to simulate a volatile nature of the data;
an integrated circuit coupled to the non-volatile memory, the integrated circuit including:
one or more agents configured to generate memory requests addressing the main memory;
a link control circuit coupled to the one or more agents and the non-volatile memory, wherein the link control circuit is configured to translate a physical address from a given agent of the one or more agents to a second physical address for the non-volatile memory;
a cryptographic circuit configured to employ one or more keys to encrypt data written to the main memory and decrypt data read from the main memory, and wherein the integrated circuit is configured to store the one or more keys within the integrated circuit and to discard the one or more keys at the power down of system to implement the non-persistent, volatile nature of the main memory; and
a control circuit configured to manage a cache formed from volatile memory, wherein the cache is configured to store main memory data to reduce latency in accessing the main memory.