US 11,714,779 B2
NoC relaxed write order scheme
Abbas Morshed, Los Altos, CA (US); Ygal Arbel, Morgan Hill, CA (US); and Eun Mi Kim, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Mar. 25, 2020, as Appl. No. 16/830,142.
Prior Publication US 2021/0303508 A1, Sep. 30, 2021
Int. Cl. G06F 15/78 (2006.01); G06F 5/10 (2006.01); G06F 9/38 (2018.01); G06F 13/40 (2006.01)
CPC G06F 15/7825 (2013.01) [G06F 5/10 (2013.01); G06F 9/38 (2013.01); G06F 13/4027 (2013.01); G06F 2205/064 (2013.01); G06F 2213/0038 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first hardware entity;
a second hardware entity;
a network on a chip (NoC) providing connectivity between the first and second hardware entities within the integrated circuit, the NoC comprising:
an ingress logic block coupled to the first hardware entity; and
an egress logic block coupled to the second hardware entity, wherein the ingress logic block comprises a write tracker configured to:
receive a first request from the first hardware entity to write data to the second hardware entity; and
determine whether the first request is one of a relaxed ordered request or a strict ordered request, wherein the relaxed ordered request can be executed in parallel with a subsequently received strict and relaxed ordered requests while the strict ordered request can be executed in parallel with a subsequently received strict ordered request that has a same destination as the first request.