US 11,714,759 B2
Private memory management using utility thread
Benjiman L. Goodman, Cedar Park, TX (US); Terence M. Potter, Austin, TX (US); Anjana Rajendran, Austin, TX (US); Mark I. Luffel, Austin, TX (US); and William V. Miller, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 17, 2020, as Appl. No. 16/995,450.
Prior Publication US 2022/0050790 A1, Feb. 17, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 12/1009 (2016.01); G06F 9/38 (2018.01); G06T 1/60 (2006.01); G06T 1/20 (2006.01)
CPC G06F 12/1009 (2013.01) [G06F 9/3887 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
graphics processor circuitry configured to:
generate a pool of private memory pages for a set of graphics work that includes multiple threads, prior to execution of the multiple threads;
maintain a translation table in memory, wherein the translation table is configured to map private memory addresses to virtual addresses based on identifiers of the threads;
execute a first thread to:
receive a request to allocate a private memory page for a second thread of the multiple threads, based on execution of a map request instruction by the second thread;
select a private memory page from the pool in response to the request; and
populate an entry in the translation table that maps the selected page for the second thread in response to the request; and
execute one or more instructions of the second thread to access a private memory space, wherein the execution includes translation of a private memory address to a virtual address based on the mapped page in the translation table.