CPC G06F 11/1016 (2013.01) [G06F 12/14 (2013.01); G06F 2212/1052 (2013.01)] | 20 Claims |
1. A memory circuit comprising:
a memory configured to store a data unit and parity bits, the parity bits including data parity bits based on the data unit and write address parity bits based on a write address associated with the stored data unit;
a write address port configured to receive the write address for the stored data unit;
a first decoding circuit configured to determine when a data error exists based on the stored data unit and the data parity bits;
a second decoding circuit configured to generate a decoded write address from a read address and the write address parity bits; and
an error detecting circuit configured to determine when an address error exists based on a comparison of the decoded write address to the read address.
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