CPC G06F 9/30145 (2013.01) [G06F 9/3017 (2013.01); G06F 9/3802 (2013.01); G06F 9/3857 (2013.01); G06F 15/7889 (2013.01)] | 10 Claims |
1. A Reduced Instruction Set Computer Five-based three dimensional (RISC-V-based 3D) interconnected multi-core processor architecture, comprising a main control layer, a micro core array layer and an accelerator layer, wherein
the main control layer comprises a plurality of main cores, the main cores are RISC-V instruction set Central Processing Unit (CPU) cores based on a five-stage pipeline, and the main cores interact with other main cores and the external environment through independent buses;
the micro core array layer comprises a plurality of micro unit groups, a micro unit comprises a micro core, a data storage unit, an instruction storage unit and a linking controller, wherein the micro core is an RISC-V instruction set CPU core that executes partial functions of the main core;
the accelerator layer is configured to optimize a running speed and space utilization for accelerators meeting specific requirements, wherein
some main cores in the main control layer perform data interaction with the accelerator layer, the other main cores interact with the micro core array layer, external simple instructions are directly processed in the main cores, and complex instructions are converted into simple instructions which are then processed by the micro cores.
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