US 11,714,642 B2
Systems, methods, and apparatuses for tile store
Robert Valentine, Kiryat Tivon (IL); Menachem Adelman, Haifa (IL); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Bret L. Toll, Hillsboro, OR (US); Milind B. Girkar, Sunnyvale, CA (US); Zeev Sperber, Zichron Yackov (IL); Mark J. Charney, Lexington, MA (US); Rinat Rappoport, Haifa (IL); Jesus Corbal, King City, OR (US); Stanislav Shwartsman, Haifa (IL); Igor Yanover, Yokneam Illit (IL); Alexander F. Heinecke, San Jose, CA (US); Barukh Ziv, Haifa (IL); Dan Baum, Haifa (IL); and Yuri Gebil, Nahariya (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 28, 2022, as Appl. No. 17/706,428.
Application 17/706,428 is a continuation of application No. 16/487,755, granted, now 11,288,069, previously published as PCT/US2017/040543, filed on Jul. 1, 2017.
Claims priority of provisional application 62/473,732, filed on Mar. 20, 2017.
Prior Publication US 2022/0291927 A1, Sep. 15, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 7/485 (2006.01); G06F 7/487 (2006.01); G06F 17/16 (2006.01); G06F 7/76 (2006.01); G06F 9/38 (2018.01)
CPC G06F 9/30036 (2013.01) [G06F 7/485 (2013.01); G06F 7/4876 (2013.01); G06F 7/762 (2013.01); G06F 9/3001 (2013.01); G06F 9/3016 (2013.01); G06F 9/30032 (2013.01); G06F 9/30043 (2013.01); G06F 9/30109 (2013.01); G06F 9/30112 (2013.01); G06F 9/30134 (2013.01); G06F 9/30145 (2013.01); G06F 9/30149 (2013.01); G06F 9/30185 (2013.01); G06F 9/30196 (2013.01); G06F 9/3818 (2013.01); G06F 9/3836 (2013.01); G06F 17/16 (2013.01); G06F 2212/454 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
decode circuitry to decode a single instruction having fields for an opcode to indicate execution circuitry is to save a context state to memory, wherein the context state is to include multidimensional matrix data of tiles according to two configuration bits, a first configuration bit to correspond to configuration data loaded in a tile configuration and the second configuration bit to correspond to matrix data; and
execution circuitry to execute the decoded single instruction to store the context state to memory.