US 11,714,571 B2
Address bit dropping to create compacted pipe address for a memory controller
Steven Fishwick, St. Albans (GB); and Lior Zimet, Kerem Maharal (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jun. 21, 2021, as Appl. No. 17/353,371.
Claims priority of provisional application 63/179,666, filed on Apr. 26, 2021.
Prior Publication US 2022/0342805 A1, Oct. 27, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0871 (2016.01); G06F 12/0882 (2016.01); G06F 12/1045 (2016.01); G06F 12/1018 (2016.01); G06F 13/16 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/061 (2013.01); G06F 3/0604 (2013.01); G06F 3/0611 (2013.01); G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 12/0238 (2013.01); G06F 12/0646 (2013.01); G06F 12/0871 (2013.01); G06F 12/0882 (2013.01); G06F 12/1018 (2013.01); G06F 12/1054 (2013.01); G06F 12/1063 (2013.01); G06F 13/1668 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A system comprising:
a plurality of memory controllers configured to control access to memory devices;
a plurality of hardware agents configured to access data in the memory devices using memory addresses;
a plurality of configuration registers; and
a communication fabric coupled to the plurality of memory controllers and the plurality of hardware agents, wherein:
the communication fabric is configured to route a memory request having a first memory address to a first memory controller of the plurality of memory controllers based on the first memory address,
a plurality of subsets of address bits of the first memory address are hashed to direct the memory request to the first memory controller at a plurality of levels of granularity,
at least one address bit in a given one of the plurality of subsets is not included in remaining ones of the plurality of subsets;
the first memory controller is configured to drop a plurality of address bits of the first memory address to form a second address used within the first memory controller, wherein the plurality of configuration registers are configured to identify, based on values programmed into the configuration registers, ones of the plurality of address that are dropped; and
respective bits of the plurality of address bits are the at least one address bit in the given one of the plurality of subsets and shifting remaining address bits of the plurality of address bits to form a compacted address used within the first memory controller.