US 10,368,442 B2
Integrated circuit structure and method of forming
Chen-Hua Yu, Hsin-Chu (TW); Jui-Pin Hung, Hsin-Chu (TW); and Kuo-Chung Yee, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Oct. 30, 2015, as Appl. No. 14/928,768.
Claims priority of provisional application 62/140,356, filed on Mar. 30, 2015.
Prior Publication US 2016/0295700 A1, Oct. 6, 2016
Int. Cl. H05K 1/18 (2006.01); H01L 21/683 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 21/56 (2006.01); H05K 3/30 (2006.01); H05K 3/34 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01)
CPC H05K 1/181 (2013.01) [H01L 21/6835 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 2221/68318 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2221/68381 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18162 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19105 (2013.01); H01L 2924/3511 (2013.01); H05K 3/301 (2013.01); H05K 3/341 (2013.01); H05K 2201/10098 (2013.01); H05K 2201/10189 (2013.01); H05K 2201/10378 (2013.01); Y02P 70/611 (2015.11); Y10T 29/4913 (2015.01)] 20 Claims
OG exemplary drawing
 
1. A method of making a semiconductor device, comprising:
placing a die over a carrier substrate;
forming a molding compound adjacent to the die;
forming one or more redistribution layers electrically coupled to the die and overlying the molding compound;
removing the carrier substrate;
connecting a first substrate to the one or more redistribution layers on an opposite side of the one or more redistribution layers from the die; and
connecting the one or more redistribution layers to a printed circuit board, wherein after the one or more redistribution layers are connected to the printed circuit board the one or more redistribution layers only partially overlap the printed circuit board, a first sidewall of the printed circuit board overlies the one or more redistribution layers, and the printed circuit board extends laterally beyond the one or more redistribution layers.