US 10,368,440 B2
Printed wiring board
Takema Adachi, Ogaki (JP); Toshihide Makino, Ogaki (JP); and Hidetoshi Noguchi, Ogaki (JP)
Assigned to IBIDEN CO., LTD., Ogaki (JP)
Filed by IBIDEN CO., LTD., Ogaki (JP)
Filed on Oct. 19, 2018, as Appl. No. 16/165,743.
Claims priority of application No. 2017-204926 (JP), filed on Oct. 24, 2017.
Prior Publication US 2019/0124765 A1, Apr. 25, 2019
Int. Cl. H05K 1/11 (2006.01); H05K 3/00 (2006.01); H05K 3/42 (2006.01); H05K 3/46 (2006.01)
CPC H05K 1/115 (2013.01) [H05K 3/0038 (2013.01); H05K 3/424 (2013.01); H05K 3/429 (2013.01); H05K 3/4644 (2013.01); H05K 2201/09827 (2013.01); H05K 2203/0723 (2013.01); H05K 2203/107 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A printed wiring board, comprising:
a core substrate comprising a core layer, a first conductor layer formed on a first surface of the core layer, a second conductor layer formed on a second surface of the core layer on an opposite side with respect to the first surface, and a plurality of through-hole conductors penetrating through the core layer and connecting the first conductor layer and the second conductor layer;
a first build-up layer comprising a first resin insulating layer formed on a first side of the core substrate, an inner side first conductor layer formed on the first resin insulating layer, an outermost first resin insulating layer formed on the inner side first conductor layer, and an outermost first conductor layer formed on the outermost first resin insulating layer; and
a second build-up layer comprising a second resin insulating layer formed on a second surface of the core substrate on an opposite side with respect to the first side of the core substrate, an inner side second conductor layer formed on the second resin insulating layer, an outermost second resin insulating layer formed on the inner side second conductor layer, and an outermost second conductor layer formed on the outermost second resin insulating layer,
wherein the core substrate and the first and second build-up layers are formed such that each of the first and second conductor layers, the inner side first and second conductor layers, and the outermost first and second conductor layers comprises a metal foil, a seed layer formed on the metal foil, and an electrolytic plating film formed on the seed layer, and includes a plurality of conductor circuits forming spaces between adjacent conductor circuits, that the inner side first conductor layer has a smallest thickness among the first and second conductor layers, the inner side first conductor layer and the outermost first and second conductor layers, and that the inner side second conductor layer has a smallest thickness among the first and second conductor layers, the inner side second conductor layer and the outermost first and second conductor layers, the conductor circuits of the first and second conductor layers, the inner side first and second conductor layers, and the outermost first and second conductor layers are formed such that the inner side first conductor layer has a smallest circuit width and a smallest space width among the inner side first conductor layer, the first and second conductor layer, the outermost first and second conductor layers, and that the inner side second conductor layer has a smallest circuit width and a smallest space width among the inner side second conductor layer, the first and second conductor layer, and the outermost first and second conductor layers.