US 10,366,967 B2
Apparatus and method for multi-die interconnection
Jean-Philippe Fricker, Los Altos, CA (US); and Philip Ferolito, Los Altos, CA (US)
Assigned to Cerebras Systems Inc., Los Altos, CA (US)
Filed by Cerebras Systems Inc., Los Altos, CA (US)
Filed on Jun. 27, 2018, as Appl. No. 16/19,882.
Claims priority of provisional application 62/536,063, filed on Jul. 24, 2017.
Prior Publication US 2019/0027466 A1, Jan. 24, 2019
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01)
CPC H01L 25/0655 (2013.01) [H01L 21/4889 (2013.01); H01L 23/5386 (2013.01); H01L 23/562 (2013.01); H01L 23/564 (2013.01); H01L 24/43 (2013.01); H01L 24/48 (2013.01); H01L 24/94 (2013.01); H01L 2224/48137 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor having multiple, interconnected die, the semiconductor comprising:
a substrate comprising a semiconductor wafer;
a plurality of die formed with the substrate;
a circuit layer formed at each of the plurality of die;
a plurality of inter-die connections that communicatively connect disparate die formed with the substrate, wherein each of the plurality of inter-die connections extends between each pair of adjacent die of the plurality of die, and wherein each of the plurality of die comprises a protective barrier comprising a seal ring that encompasses a periphery of each of the plurality of die,
wherein the plurality of die includes:
(i) a first subset of interior die defining an interior of the substrate, wherein the first subset of interior die has inter-die connections with adjacent die along all sides of the first subset of die;
(ii) a second subset of peripheral die defining a periphery of the substrate, wherein at least one side of each of the second subset of exterior die are formed without inter-die connections.