US 11,711,811 B2
Multiplexing control information in a physical uplink data channel
Aris Papasakellariou, Houston, TX (US)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 30, 2021, as Appl. No. 17/305,157.
Application 17/305,157 is a continuation of application No. 17/303,160, filed on May 21, 2021.
Application 17/303,160 is a continuation of application No. 16/676,298, filed on Nov. 6, 2019, granted, now 11,019,607, issued on May 25, 2021.
Application 16/676,298 is a continuation of application No. 15/820,051, filed on Nov. 21, 2017, granted, now 10,492,184, issued on Nov. 26, 2019.
Claims priority of provisional application 62/509,831, filed on May 23, 2017.
Claims priority of provisional application 62/469,843, filed on Mar. 10, 2017.
Claims priority of provisional application 62/436,705, filed on Dec. 20, 2016.
Claims priority of provisional application 62/432,215, filed on Dec. 9, 2016.
Prior Publication US 2021/0329626 A1, Oct. 21, 2021
Int. Cl. H04W 72/21 (2023.01); H04L 5/00 (2006.01); H04L 1/1812 (2023.01); H04L 1/00 (2006.01); H04L 1/18 (2023.01); H04L 1/1607 (2023.01); H04L 1/1829 (2023.01); H04L 1/1867 (2023.01); H04W 88/02 (2009.01); H04W 88/08 (2009.01); H04L 1/1822 (2023.01)
CPC H04W 72/21 (2023.01) [H04L 1/00 (2013.01); H04L 1/1671 (2013.01); H04L 1/18 (2013.01); H04L 1/1812 (2013.01); H04L 1/1854 (2013.01); H04L 1/1861 (2013.01); H04L 1/1887 (2013.01); H04L 5/0053 (2013.01); H04L 5/0055 (2013.01); H04L 5/0091 (2013.01); H04L 1/1822 (2013.01); H04L 1/1864 (2013.01); H04L 5/001 (2013.01); H04L 5/0023 (2013.01); H04L 5/0035 (2013.01); H04L 5/0046 (2013.01); H04L 5/0057 (2013.01); H04W 88/02 (2013.01); H04W 88/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
determining that a first number of control information bits is smaller than a predetermined number of bits;
appending a second number of bits, each having a zero value, to the first number of control information bits, wherein the second number of bits is equal to a difference between the first number of control information bits and the predetermined number of bits;
computing first cyclic redundancy check (CRC) bits for the first number of control information bits and the second number of bits; and
encoding the first number of control information bits, the second number of bits, and the first CRC bits using a polar code.