CPC H04W 72/21 (2023.01) [H04L 1/00 (2013.01); H04L 1/1671 (2013.01); H04L 1/18 (2013.01); H04L 1/1812 (2013.01); H04L 1/1854 (2013.01); H04L 1/1861 (2013.01); H04L 1/1887 (2013.01); H04L 5/0053 (2013.01); H04L 5/0055 (2013.01); H04L 5/0091 (2013.01); H04L 1/1822 (2013.01); H04L 1/1864 (2013.01); H04L 5/001 (2013.01); H04L 5/0023 (2013.01); H04L 5/0035 (2013.01); H04L 5/0046 (2013.01); H04L 5/0057 (2013.01); H04W 88/02 (2013.01); H04W 88/08 (2013.01)] | 19 Claims |
1. A method, comprising:
determining that a first number of control information bits is smaller than a predetermined number of bits;
appending a second number of bits, each having a zero value, to the first number of control information bits, wherein the second number of bits is equal to a difference between the first number of control information bits and the predetermined number of bits;
computing first cyclic redundancy check (CRC) bits for the first number of control information bits and the second number of bits; and
encoding the first number of control information bits, the second number of bits, and the first CRC bits using a polar code.
|