CPC H03M 13/1108 (2013.01) [H03M 13/1177 (2013.01); H03M 13/1575 (2013.01); H03M 13/2948 (2013.01)] | 20 Claims |
1. A device, comprising:
memory cells; and
a logic circuit configured to:
obtain a codeword represented by states of the memory cells;
perform bit flipping decoding of the codeword according to a first mode of selecting bits for flipping;
detect a pattern in parity violations of the codeword in the bit flipping decoding according to the first mode; and
change, in response to detection of the pattern, from the first mode of selecting bits for flipping to a second mode of selecting bits for flipping in the bit flipping decoding.
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