US 11,711,095 B2
Bit flipping low-density parity-check decoders with low error floor
Mustafa N. Kaynak, San Diego, CA (US); and Sivagnanam Parthasarathy, Carlsbad, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 26, 2022, as Appl. No. 17/729,775.
Application 17/729,775 is a continuation of application No. 17/066,384, filed on Oct. 8, 2020, granted, now 11,349,498.
Prior Publication US 2022/0255561 A1, Aug. 11, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01); H03M 13/29 (2006.01); H03M 13/15 (2006.01)
CPC H03M 13/1108 (2013.01) [H03M 13/1177 (2013.01); H03M 13/1575 (2013.01); H03M 13/2948 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
memory cells; and
a logic circuit configured to:
obtain a codeword represented by states of the memory cells;
perform bit flipping decoding of the codeword according to a first mode of selecting bits for flipping;
detect a pattern in parity violations of the codeword in the bit flipping decoding according to the first mode; and
change, in response to detection of the pattern, from the first mode of selecting bits for flipping to a second mode of selecting bits for flipping in the bit flipping decoding.