US 11,711,071 B2
Current mode control modulator including ramp signal generator providing slope compensation
Nicholas I. Archibald, San Francisco, CA (US); Rhys S. A. Philbrick, Los Gatos, CA (US); and Steven P. Laur, Raleigh, NC (US)
Assigned to Alpha and Omega Semiconductor (Cayman) Ltd., Grand Cayman (KY)
Filed by Alpha and Omega Semiconductor (Cayman) Ltd., Grand Cayman (KY)
Filed on Nov. 1, 2021, as Appl. No. 17/515,550.
Application 17/515,550 is a continuation of application No. 17/035,012, filed on Sep. 28, 2020, granted, now 11,196,409.
Application 17/035,012 is a continuation of application No. 16/703,715, filed on Dec. 4, 2019, granted, now 10,833,661, issued on Nov. 10, 2020.
Prior Publication US 2022/0052675 A1, Feb. 17, 2022
Int. Cl. H03K 3/017 (2006.01); H03K 4/08 (2006.01); H03K 3/037 (2006.01)
CPC H03K 4/08 (2013.01) [H03K 3/017 (2013.01); H03K 3/037 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A current mode control modulator generating a pulse width modulation (PWM) signal in response to a feedback voltage signal indicative of a regulated output voltage generated from an input voltage, the current mode control modulator comprising:
a first error amplifier receiving the feedback voltage signal indicative of the regulated output voltage and a target voltage, the first error amplifier generating a signal indicative of a difference between the feedback voltage signal and the target voltage on an output terminal;
a modulating comparator having a first input terminal receiving the signal indicative of the difference and a second input terminal receiving a current loop signal indicative of an expected current level, the modulating comparator having an output terminal generating a reset signal;
a latch circuit having a reset input terminal coupled to receive the reset signal from the modulating comparator, a set input terminal coupled to receive a clock signal, and an output terminal generating the PWM signal, the PWM signal having an on-duration defining a duty cycle of the PWM signal and an off-duration, wherein the set signal initiates the on-duration of the PWM signal and the reset signal terminates the on-duration of the PWM signal; and
a ramp signal generator circuit receiving the PWM signal and generating a slope compensated ramp signal as the current loop signal, the ramp signal generator comprising a switched capacitor circuit supplied by a current circuit to charge or discharge nodes in the switched capacitor circuit, wherein the ramp signal generator generates the slope compensated ramp signal having a first ramp portion by using the switched capacitor circuit to divide a charge associated with the expected current level during a first duration of the PWM signal, and the ramp signal generator further generates the slope compensated ramp signal having a second ramp portion by using the switched capacitor circuit to accumulate the charge associated with the expected current level during a second duration of the PWM signal.