US 11,710,787 B2
Laterally diffused metal oxide semiconductor device and method for manufacturing the same
Budong You, Hangzhou (CN); Hui Yu, Hangzhou (CN); Meng Wang, Hangzhou (CN); Yicheng Du, Hangzhou (CN); Chuan Peng, Hangzhou (CN); and Xianguo Huang, Hangzhou (CN)
Assigned to Silergy Semiconductor Technology (Hangzhou) LTD, Hangzhou (CN)
Filed by Silergy Semiconductor Technology (Hangzhou) LTD, Hangzhou (CN)
Filed on Aug. 12, 2021, as Appl. No. 17/400,287.
Application 17/400,287 is a continuation of application No. 16/412,587, filed on May 15, 2019, granted, now 11,121,251.
Claims priority of application No. 201810515185.8 (CN), filed on May 25, 2018.
Prior Publication US 2021/0376144 A1, Dec. 2, 2021
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 29/063 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01); H01L 29/66681 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method of manufacturing a laterally diffused metal oxide semiconductor device, the method comprising:
a) forming a source region and a drain region in a base layer;
b) forming a first dielectric layer on a top surface of the base layer, wherein the first dielectric layer is adjacent to the source region;
c) forming a voltage withstanding layer between the first dielectric layer and the drain region;
d) forming a conductor layer on the first dielectric layer and the voltage withstanding layer;
e) forming a first conductor at least partially located on the first dielectric layer, a second conductor at least partially located on the voltage withstanding layer, and a plurality of third conductors that are spatially isolated and located on the voltage withstanding layer, by etching the conductor layer;
f) forming a gate electrode electrically connected to the first conductor and a first field plate electrode electrically connected to the second conductor; and
g) forming a source electrode electrically connected to the source region,
h) wherein the first and second conductors are spatially isolated, and the source electrode at least covers a space between the first and second conductors and a space between the second conductor and an adjacent one of the plurality of third conductors.