CPC H01L 21/823462 (2013.01) [H01L 21/02356 (2013.01); H01L 21/28158 (2013.01); H01L 21/28185 (2013.01); H01L 21/3115 (2013.01); H01L 21/823431 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
1. A method comprising:
forming a gate dielectric layer over a channel region of a semiconductor fin, wherein the gate dielectric layer comprises nano-crystallite regions separated by an amorphous matrix material;
performing a first anneal process to modify a first crystalline structure of the gate dielectric layer to a second crystalline structure, wherein after the first anneal process each of the nano-crystallite regions has a crystallite size with a first cross-sectional diameter;
performing a second anneal process to modify the second crystalline structure of the gate dielectric layer to a third crystalline structure, wherein after the second anneal process each of the nano-crystallite regions has a crystallite size with a second cross-sectional diameter, wherein the second cross-sectional diameter is larger than the first cross-sectional diameter; and
depositing a capping layer over the gate dielectric layer after the first anneal process and prior to the second anneal process.
|