US 11,710,665 B2
Semiconductor device and method of manufacture
Chun-Yen Peng, Hsinchu (TW); Te-Yang Lai, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); and Chi On Chui, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 16, 2021, as Appl. No. 17/403,263.
Application 17/403,263 is a continuation of application No. 16/549,536, filed on Aug. 23, 2019, granted, now 11,101,180.
Prior Publication US 2021/0375690 A1, Dec. 2, 2021
Int. Cl. H01L 21/8234 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 21/3115 (2006.01)
CPC H01L 21/823462 (2013.01) [H01L 21/02356 (2013.01); H01L 21/28158 (2013.01); H01L 21/28185 (2013.01); H01L 21/3115 (2013.01); H01L 21/823431 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a gate dielectric layer over a channel region of a semiconductor fin, wherein the gate dielectric layer comprises nano-crystallite regions separated by an amorphous matrix material;
performing a first anneal process to modify a first crystalline structure of the gate dielectric layer to a second crystalline structure, wherein after the first anneal process each of the nano-crystallite regions has a crystallite size with a first cross-sectional diameter;
performing a second anneal process to modify the second crystalline structure of the gate dielectric layer to a third crystalline structure, wherein after the second anneal process each of the nano-crystallite regions has a crystallite size with a second cross-sectional diameter, wherein the second cross-sectional diameter is larger than the first cross-sectional diameter; and
depositing a capping layer over the gate dielectric layer after the first anneal process and prior to the second anneal process.