US 11,710,661 B2
Semiconductor packages and methods of packaging semiconductor devices
Enrique Jr Sarile, Singapore (SG); Dzafir Bin Mohd Shariff, Singapore (SG); Seung Geun Park, Singapore (SG); Ronnie M. De Villa, Singapore (SG); and Zhong Hai Wang, Singapore (SG)
Assigned to UTAC Headquarters Pte. Ltd, Singapore (SG)
Filed by UTAC Headquarters Pte. Ltd., Singapore (SG)
Filed on Oct. 15, 2020, as Appl. No. 17/72,006.
Claims priority of provisional application 62/916,792, filed on Oct. 17, 2019.
Prior Publication US 2021/0118738 A1, Apr. 22, 2021
Int. Cl. H01L 21/78 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/78 (2013.01) [H01L 23/3192 (2013.01); H01L 23/564 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a die having a top die surface, a bottom die surface and die sidewall surfaces, wherein the bottom die surface comprises a backside wafer surface on which the die is formed, the top die surface comprises an active surface of the die
a passivation layer over the top die surface
backside metallization (BSM) on the bottom die surface, wherein
die sidewalls and passivation sidewalls of the passivation layer are recessed from BSM sidewalls of the BSM,
a top portion of the BSM sidewalls comprises deburred top BSM portions of the BSM sidewalls, wherein the deburred top BSM portions of the BSM sidewalls comprise beveled top BSM sidewall surfaces, and
sidewall profiles of the semiconductor package are defined by the BSM sidewalls, die sidewalls and passivation sidewalls.