CPC G11C 16/34 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01); G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/079 (2013.01); G06F 11/0793 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); G11C 16/3445 (2013.01); G11C 16/3459 (2013.01); G11C 29/00 (2013.01); G11C 29/84 (2013.01); G11C 16/0483 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2272 (2013.01); G11C 2207/2281 (2013.01)] | 20 Claims |
1. A system comprising:
a memory; and
a processing device communicably coupled to the memory, the processing device to:
determine that a first programming operation has been performed on a particular memory cell;
determine, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate; and
in response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, perform an operation on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.
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