US 11,710,527 B2
Mitigating a voltage condition of a memory cell in a memory sub-system
Vamsi Pavan Rayaprolu, San Jose, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); Peter Feeley, Boise, ID (US); Sampath K. Ratnam, Boise, ID (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Qisong Lin, El Dorado Hills, CA (US); Shane Nowell, Boise, ID (US); and Mustafa N. Kaynak, San Diego, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 19, 2022, as Appl. No. 17/868,685.
Application 17/129,627 is a division of application No. 16/045,641, filed on Jul. 25, 2018, granted, now 10,872,009, issued on Dec. 22, 2020.
Application 17/868,685 is a continuation of application No. 17/129,627, filed on Dec. 21, 2020, granted, now 11,393,541, issued on Jul. 19, 2022.
Claims priority of provisional application 62/628,198, filed on Feb. 8, 2018.
Prior Publication US 2022/0351786 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 29/00 (2006.01); G06F 11/07 (2006.01); G11C 16/26 (2006.01); G06F 3/06 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/34 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01); G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/079 (2013.01); G06F 11/0793 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); G11C 16/3445 (2013.01); G11C 16/3459 (2013.01); G11C 29/00 (2013.01); G11C 29/84 (2013.01); G11C 16/0483 (2013.01); G11C 2207/229 (2013.01); G11C 2207/2272 (2013.01); G11C 2207/2281 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory; and
a processing device communicably coupled to the memory, the processing device to:
determine that a first programming operation has been performed on a particular memory cell;
determine, based on one or more threshold criteria, whether the particular memory cell has transitioned from a state associated with a decreased error rate to another state associated with an increased error rate; and
in response to determining that the particular memory cell has transitioned from the state associated with the decreased error rate to the another state associated with the increased error rate, perform an operation on the particular memory cell to transition the particular memory cell from the another state associated with the increased error rate to the state associated with the decreased error rate.