US 11,710,517 B2
Write operation techniques for memory systems
Zhongyuan Lu, Boise, ID (US); Christina Papagianni, San Jose, CA (US); Hongmei Wang, Boise, ID (US); and Robert J. Gleixner, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 5, 2022, as Appl. No. 17/569,295.
Application 17/569,295 is a continuation of application No. 16/700,948, filed on Dec. 2, 2019, granted, now 11,244,717.
Prior Publication US 2022/0130444 A1, Apr. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/406 (2006.01); G11C 11/409 (2006.01); G11C 7/22 (2006.01); G11C 11/56 (2006.01); G11C 11/408 (2006.01)
CPC G11C 11/409 (2013.01) [G11C 7/222 (2013.01); G11C 11/4082 (2013.01); G11C 11/5628 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
refraining from writing information to a plurality of memory cells of a memory array for a first duration based at least in part on a quantity of write operations performed on the plurality of memory cells;
performing at least one read operation on the plurality of memory cells of the memory array during the first duration; and
writing information to the plurality of memory cells of the memory array after the first duration.