US 11,709,734 B2
Error correction with syndrome computation in a memory device
Mustafa N. Kaynak, San Diego, CA (US); Patrick R. Khayat, San Diego, CA (US); and Sivagnanam Parthasarathy, Carlsbad, CA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 30, 2021, as Appl. No. 17/246,509.
Prior Publication US 2022/0350700 A1, Nov. 3, 2022
Int. Cl. G06F 11/10 (2006.01); G06F 11/00 (2006.01); H03M 13/00 (2006.01)
CPC G06F 11/1076 (2013.01) 20 Claims
OG exemplary drawing
 
1. A method comprising:
generating, in a memory device that stores a plurality of encoded data, a first syndrome for a first encoded data from the plurality of encoded data;
transmitting the first encoded data and the first syndrome to a controller that is coupled with the memory device;
generating, in the memory device, a second syndrome for the first encoded data and a second encoded data from the plurality of encoded data, wherein the first encoded data and the second encoded data are interrelated according to an error correction code; and
transmitting the second syndrome to the controller without the second encoded data, wherein the controller is to decode the first encoded data based on at least one of the first syndrome, the second syndrome, or a combination thereof.