US 11,709,727 B2
Managing error-handling flows in memory devices
Kishore Kumar Muchherla, Fremont, CA (US); Shane Nowell, Boise, ID (US); Mustafa N. Kaynak, San Diego, CA (US); Sampath K. Ratnam, Boise, ID (US); Peter Feeley, Boise, ID (US); Sivagnanam Parthasarathy, Carlsbad, CA (US); Devin M. Batutis, San Jose, CA (US); and Xiangang Luo, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 30, 2021, as Appl. No. 17/216,901.
Prior Publication US 2022/0318086 A1, Oct. 6, 2022
Int. Cl. G06F 11/00 (2006.01); G06F 11/07 (2006.01)
CPC G06F 11/0793 (2013.01) [G06F 11/0727 (2013.01); G06F 11/0751 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, to perform operations comprising:
detecting a read error with respect to data residing in a block of the memory device, wherein the block is associated with a voltage offset bin;
determining an ordered set of error-handling operations to be performed to the data;
determining a most recently performed error-handling operation associated with the voltage offset bin, wherein the most recently performed error-handling operation is an error-handling operation that has successfully recovered data associated with a previous read error that occurred to a block associated with the voltage offset bin;
adjusting an order of the set of error-handling operations by positioning the most recently performed error-handling operation within a predetermined position in the order of the set of error-handling operations; and
performing one or more error-handling operations of the set of error-handling operations in the adjusted order until data associated to the read error is recovered.