US 11,709,633 B2
Adjusting scan event thresholds to mitigate memory errors
Gianni Stephen Alsasua, Rancho Cordova, CA (US); Harish Reddy Singidi, Fremont, CA (US); Peter Sean Feeley, Boise, ID (US); Ashutosh Malshe, Fremont, CA (US); Renato Padilla, Jr., Folsom, CA (US); Kishore Kumar Muchherla, Fremont, CA (US); and Sampath Ratnam, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 2, 2022, as Appl. No. 17/685,102.
Application 17/685,102 is a continuation of application No. 16/878,304, filed on May 19, 2020, granted, now 11,269,553.
Application 16/878,304 is a continuation of application No. 16/138,334, filed on Sep. 21, 2018, granted, now 10,691,377.
Prior Publication US 2022/0188040 A1, Jun. 16, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G11C 16/34 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/064 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 16/3422 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a first group of memory cells and a second group of memory cells, the first group of memory cells being separate from the second group of memory cells; and
a processing device operably coupled to the memory device, the processing device configured to perform operations comprising:
skewing a first read count value for the first group of memory cells from a first actual read count value of the first group of memory cells;
triggering at least one of a first scan event or a first fold event for the first group of memory cells based on the skewed first read count value and an event threshold; and
triggering at least one of a second scan event or a second fold event for the second group of memory cells based on a second read count value and the event threshold, the second read count value comprising a second actual read count value for the second group of memory cells.