CPC G06F 3/064 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0631 (2013.01); G06F 3/0632 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] | 19 Claims |
1. A memory controller for controlling a memory device including a plurality of memory blocks allocated to a plurality of zones, the memory controller comprising:
a plurality of cores configured to control the plurality of zones;
a reset information controller configured to generate reset count values representing a number of a reset request input with respect to the plurality of zones, in response to the reset request input from a host, and configured to generate reset count sum values obtained by summing the reset count values of a plurality of zones controlled by each of the plurality of cores; and
a wear level manager configured to control the plurality of cores such that a core that is different from a first core having a highest reset count sum value from among the plurality of cores controls some of a plurality of zones controlled by the first core according to whether a difference value between the highest reset count sum value and a lowest reset count sum value from among the reset count sum values exceeds a threshold difference value.
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