US 11,709,606 B2
Memory controller and operating method thereof
Gyung Min Park, Icheon-si (KR); Keon Yeong Lee, Icheon-si (KR); and Jae Gwang Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Feb. 9, 2021, as Appl. No. 17/171,511.
Claims priority of application No. 10-2020-0105527 (KR), filed on Aug. 21, 2020.
Prior Publication US 2022/0057938 A1, Feb. 24, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/064 (2013.01) [G06F 3/0614 (2013.01); G06F 3/0631 (2013.01); G06F 3/0632 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory controller for controlling a memory device including a plurality of memory blocks allocated to a plurality of zones, the memory controller comprising:
a plurality of cores configured to control the plurality of zones;
a reset information controller configured to generate reset count values representing a number of a reset request input with respect to the plurality of zones, in response to the reset request input from a host, and configured to generate reset count sum values obtained by summing the reset count values of a plurality of zones controlled by each of the plurality of cores; and
a wear level manager configured to control the plurality of cores such that a core that is different from a first core having a highest reset count sum value from among the plurality of cores controls some of a plurality of zones controlled by the first core according to whether a difference value between the highest reset count sum value and a lowest reset count sum value from among the reset count sum values exceeds a threshold difference value.