US 11,709,522 B1
Power and temperature driven clock throttling
Sebastian Turullols, Los Altos, CA (US); Ravinder Sharma, Hyderabad (IN); Siva Santosh Kumar Pyla, Hyderabad (IN); Raj Kumar Rampelli, Hyderabad (IN); Deboleena Minz Sakalley, Hyderabad (IN); and Nilay Shah, Thane (IN)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Sep. 16, 2020, as Appl. No. 17/23,016.
Int. Cl. G06F 1/26 (2006.01); G06F 1/08 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/26 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A peripheral device comprising:
a communication interface configured to couple to a host;
a dynamic clock configured to generate a clock signal that changes based on at least one of a power consumption in the peripheral device or a temperature of the peripheral device, wherein the dynamic clock comprises:
a static clock source that produces a static clock signal with an initial clock rate of a fixed frequency,
a plurality of pattern registers that hold a pattern that indicates what portions of the static clock signal are to be skipped,
clock skipping logic configured to generate a clock enable signal based on the pattern stored in the plurality of pattern registers, and
a clock enable pin configured to receive the static clock signal and output, in response to the clock enable signal, the clock signal with a dynamic clock rate less than the initial clock rate; and
computing resources configured to perform operations offloaded from the host to the peripheral device via the communication interface, wherein the operations are performed at a performance rate set by the clock signal.