US 11,707,000 B2
Side-gating in selective-area-grown topological qubits
Dmitry Pikulin, Goleta, CA (US); Michael H. Freedman, Santa Barbara, CA (US); Roman Lutchyn, Santa Barbara, CA (US); Peter Krogstrup Jeppesen, Frederiksberg (DK); and Parsa Bonderson, Santa Barbara, CA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Appl. No. 16/756,437
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
PCT Filed Jun. 27, 2018, PCT No. PCT/US2018/039833
§ 371(c)(1), (2) Date Apr. 15, 2020,
PCT Pub. No. WO2019/074557, PCT Pub. Date Apr. 18, 2019.
Claims priority of provisional application 62/572,560, filed on Oct. 15, 2017.
Prior Publication US 2020/0287120 A1, Sep. 10, 2020
Int. Cl. H10N 60/01 (2023.01); G06N 10/00 (2022.01); H10N 60/84 (2023.01); H10N 60/10 (2023.01)
CPC H10N 60/01 (2023.02) [G06N 10/00 (2019.01); H10N 60/128 (2023.02); H10N 60/84 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method for fabricating a quantum device, the method comprising:
providing a substrate and an insulator formed on the substrate;
from combinations of selective-area-grown semiconductor material along with regions of a superconducting material, forming a network of nanowires oriented in a plane of the substrate that is gateable to produce a Majorana-based topological qubit; and
fabricating a side gate for controlling a topological segment of the Majorana-based topological qubit;
wherein the selective-area-grown semiconductor material is grown on the substrate by etching trenches in the insulator formed on the substrate to define the nanowires and depositing the semiconductor material in the trenches defining the nanowires; and
wherein the fabricating of the side gate comprises etching the insulator to create a trench for the side gate and depositing the side gate in the trench for the side gate.