US 11,706,909 B2
Integrated assemblies comprising memory cells and shielding material between the memory cells
Sanh D. Tang, Boise, ID (US); Mitsunari Sukekawa, Hiroshima (JP); Yusuke Yamamoto, Hiroshima (JP); Christopher J. Kawamura, Boise, ID (US); and Hiroaki Taketani, Hiroshima (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 28, 2020, as Appl. No. 17/83,174.
Application 17/083,174 is a division of application No. 16/354,450, filed on Mar. 15, 2019, granted, now 10,910,379.
Prior Publication US 2021/0074705 A1, Mar. 11, 2021
Int. Cl. H10B 12/00 (2023.01); H01L 23/528 (2006.01)
CPC H10B 12/31 (2023.02) [H01L 23/5283 (2013.01); H10B 12/033 (2023.02); H10B 12/05 (2023.02); H10B 12/488 (2023.02)] 24 Claims
OG exemplary drawing
 
1. An assembly, comprising:
a semiconductor material having a horizontal surface;
a row of vertically-extending semiconductor pillars over the horizontal surface; each of the semiconductor pillars comprising a transistor channel region vertically disposed between a first source/drain region and a second source/drain region;
a wordline extending along the row of vertically-extending semiconductor pillars, and being adjacent to the transistor channel regions of the semiconductor pillars; the wordline having a first lateral surface and an opposing second lateral surface; the semiconductor pillars being subdivided amongst a first set along the first lateral surface, and a second set along the second lateral surface; the semiconductor pillars of the first set alternating with the semiconductor pillars of the second set along the row;
a gate dielectric material between the first lateral surface and the transistor channel regions of the semiconductor pillars of the first set, and between the second lateral surface and the transistor channel regions of the semiconductor pillars of the second set;
a conductive shield material between the semiconductor pillars of the first set, and between the semiconductor pillars of the second set;
bitlines coupled with the first source/drain regions; and
storage elements coupled with the second source/drain regions.