CPC H04W 56/001 (2013.01) [H04L 27/2613 (2013.01); H04L 27/2634 (2013.01); H04W 4/80 (2018.02); H04L 27/26132 (2021.01)] | 25 Claims |
1. A communication device comprising:
a transmit circuitry;
a receive circuitry;
an antenna coupled to the transmit circuitry and to the receive circuitry, the receive circuitry configured to receive, using the antenna, a first packet having first data symbols;
a processor that includes:
a first set of circuitry configured to process real symbols; and
a second set of circuitry configured to process complex symbols; and
a non-transitory machine-readable storage medium comprising executable instructions that, when executed, cause the processor to:
generate, based on the first data symbols, second data symbols comprising no complex portions;
generate, using the first set of circuitry of the processor and without using the second set of circuitry of the processor, a synchronization header based on the second data symbols, wherein the synchronization header includes a short training field (STF) and a long training field (LTF), wherein the STF and the LTF are arranged directly adjacent to one another within the synchronization header;
generate a second packet that includes the synchronization header, a packet header, and a packet payload; and
cause the transmit circuitry to transmit the second packet over a network using the antenna.
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