US 11,706,725 B2
Short and long training fields
Timothy M. Schmidl, Dallas, TX (US); Anuj Batra, Dallas, TX (US); and Srinath Hosur, Plano, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Oct. 16, 2020, as Appl. No. 17/72,232.
Application 17/072,232 is a continuation of application No. 16/044,074, filed on Jul. 24, 2018, granted, now 10,813,064.
Application 16/044,074 is a continuation of application No. 14/025,628, filed on Sep. 12, 2013, granted, now 10,034,252.
Application 14/025,628 is a continuation of application No. 12/868,397, filed on Aug. 25, 2010, granted, now 8,553,730, issued on Oct. 8, 2013.
Claims priority of provisional application 61/287,586, filed on Dec. 17, 2009.
Claims priority of provisional application 61/238,445, filed on Aug. 31, 2009.
Prior Publication US 2021/0037491 A1, Feb. 4, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H04W 56/00 (2009.01); H04L 27/26 (2006.01); H04W 4/80 (2018.01)
CPC H04W 56/001 (2013.01) [H04L 27/2613 (2013.01); H04L 27/2634 (2013.01); H04W 4/80 (2018.02); H04L 27/26132 (2021.01)] 25 Claims
OG exemplary drawing
 
1. A communication device comprising:
a transmit circuitry;
a receive circuitry;
an antenna coupled to the transmit circuitry and to the receive circuitry, the receive circuitry configured to receive, using the antenna, a first packet having first data symbols;
a processor that includes:
a first set of circuitry configured to process real symbols; and
a second set of circuitry configured to process complex symbols; and
a non-transitory machine-readable storage medium comprising executable instructions that, when executed, cause the processor to:
generate, based on the first data symbols, second data symbols comprising no complex portions;
generate, using the first set of circuitry of the processor and without using the second set of circuitry of the processor, a synchronization header based on the second data symbols, wherein the synchronization header includes a short training field (STF) and a long training field (LTF), wherein the STF and the LTF are arranged directly adjacent to one another within the synchronization header;
generate a second packet that includes the synchronization header, a packet header, and a packet payload; and
cause the transmit circuitry to transmit the second packet over a network using the antenna.