CPC H04N 19/124 (2014.11) [G06T 9/00 (2013.01); G06T 9/005 (2013.01); G06T 9/007 (2013.01); G06T 9/008 (2013.01); H04N 19/13 (2014.11); H04N 19/134 (2014.11); H04N 19/17 (2014.11); H04N 19/172 (2014.11); H04N 19/174 (2014.11); H04N 19/176 (2014.11); H04N 19/436 (2014.11); H04N 19/46 (2014.11); H04N 19/503 (2014.11); H04N 19/51 (2014.11); H04N 19/593 (2014.11); H04N 19/60 (2014.11); H04N 19/70 (2014.11)] | 2 Claims |
1. An image decoding apparatus, comprising:
one or more memories; and
circuitry that executes operations, the operations comprising:
obtaining pieces of coded data included in a bitstream, the pieces of coded data being generated by coding tiles, the tiles being obtained by dividing a picture; and
decoding the pieces of coded data to generate image data of the tiles,
wherein in the obtaining of the pieces of coded data, tile boundary independence information is further obtained from the bitstream, the tile boundary independence information indicating whether each of boundaries between the tiles is one of a first boundary or a second boundary, and
the decoding of the pieces of coded data includes:
generating image data of a first tile, which is one of the tiles, by decoding a first code string included in first coded data with reference to decoding information of a decoded tile, which is another one of the tiles, when the tile boundary independence information indicates the first boundary, and by decoding the first code string without referring to the decoding information of the decoded tile when the tile boundary independence information indicates the second boundary, the first coded data being one of the pieces of coded data.
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