US 11,706,416 B2
Image coding apparatus for coding tile boundaries
Daisaku Komiya, Tokyo (JP); Takahiro Nishi, Nara (JP); Youji Shibahara, Osaka (JP); Hisao Sasai, Osaka (JP); Toshiyasu Sugio, Osaka (JP); Kyoko Tanikawa, Osaka (JP); and Toru Matsunobu, Osaka (JP)
Assigned to SUN PATENT TRUST, New York, NY (US)
Filed by Sun Patent Trust, New York, NY (US)
Filed on Dec. 2, 2021, as Appl. No. 17/540,817.
Application 17/540,817 is a continuation of application No. 16/897,938, filed on Jun. 10, 2020, granted, now 11,228,765.
Application 16/897,938 is a continuation of application No. 16/530,137, filed on Aug. 2, 2019, granted, now 10,715,808, issued on Jul. 14, 2020.
Application 16/530,137 is a continuation of application No. 15/991,061, filed on May 29, 2018, granted, now 10,412,389, issued on Sep. 10, 2019.
Application 15/991,061 is a continuation of application No. 15/469,611, filed on Mar. 27, 2017, granted, now 10,009,609, issued on Jun. 26, 2018.
Application 15/469,611 is a continuation of application No. 15/142,007, filed on Apr. 29, 2016, granted, now 9,648,328, issued on May 9, 2017.
Application 15/142,007 is a continuation of application No. 14/492,587, filed on Sep. 22, 2014, granted, now 9,355,467, issued on May 31, 2016.
Application 14/492,587 is a continuation of application No. 14/090,592, filed on Nov. 26, 2013, granted, now 8,879,860, issued on Nov. 4, 2014.
Application 14/090,592 is a continuation of application No. 13/568,444, filed on Aug. 7, 2012, granted, now 8,620,097, issued on Dec. 31, 2013.
Claims priority of provisional application 61/522,382, filed on Aug. 11, 2011.
Prior Publication US 2022/0094934 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06V 10/00 (2022.01); H04N 19/124 (2014.01); H04N 19/46 (2014.01); H04N 19/13 (2014.01); H04N 19/134 (2014.01); H04N 19/436 (2014.01); H04N 19/503 (2014.01); H04N 19/176 (2014.01); H04N 19/70 (2014.01); H04N 19/172 (2014.01); H04N 19/51 (2014.01); H04N 19/60 (2014.01); H04N 19/593 (2014.01); H04N 19/174 (2014.01); H04N 19/17 (2014.01); G06T 9/00 (2006.01)
CPC H04N 19/124 (2014.11) [G06T 9/00 (2013.01); G06T 9/005 (2013.01); G06T 9/007 (2013.01); G06T 9/008 (2013.01); H04N 19/13 (2014.11); H04N 19/134 (2014.11); H04N 19/17 (2014.11); H04N 19/172 (2014.11); H04N 19/174 (2014.11); H04N 19/176 (2014.11); H04N 19/436 (2014.11); H04N 19/46 (2014.11); H04N 19/503 (2014.11); H04N 19/51 (2014.11); H04N 19/593 (2014.11); H04N 19/60 (2014.11); H04N 19/70 (2014.11)] 2 Claims
OG exemplary drawing
 
1. An image decoding apparatus, comprising:
one or more memories; and
circuitry that executes operations, the operations comprising:
obtaining pieces of coded data included in a bitstream, the pieces of coded data being generated by coding tiles, the tiles being obtained by dividing a picture; and
decoding the pieces of coded data to generate image data of the tiles,
wherein in the obtaining of the pieces of coded data, tile boundary independence information is further obtained from the bitstream, the tile boundary independence information indicating whether each of boundaries between the tiles is one of a first boundary or a second boundary, and
the decoding of the pieces of coded data includes:
generating image data of a first tile, which is one of the tiles, by decoding a first code string included in first coded data with reference to decoding information of a decoded tile, which is another one of the tiles, when the tile boundary independence information indicates the first boundary, and by decoding the first code string without referring to the decoding information of the decoded tile when the tile boundary independence information indicates the second boundary, the first coded data being one of the pieces of coded data.