| CPC H04L 7/0012 (2013.01) | 26 Claims |
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1. A synchronized communication system, comprising:
a plurality of compute nodes including a first compute node, one or more intermediate compute nodes, and a last compute node; and
clock connections to connect the compute nodes in a closed loop configuration, wherein:
each of the compute nodes has an output connected to an input of a next one of the compute nodes via a respective one of the clock connections, while the last compute node has an output connected to an input of the first compute node via another respective one of the clock connections;
the compute nodes are configured to distribute among the compute nodes, via ones of the clock connections, a master clock frequency from any selected one of the compute nodes, which is designated as a master clock;
at a first time one of the plurality of compute nodes is designated as the master clock and is configured to distribute the master clock frequency among the compute nodes; and
at a second time another one of the plurality of compute nodes is designated as the master clock, and is configured to distribute the master clock frequency among the compute nodes.
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