US 11,705,925 B2
Dynamic bit flipping order for iterative error correction
Mustafa N. Kaynak, San Diego, CA (US); and Sivagnanam Parthasarathy, Carlsbad, CA (US)
Assigned to MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/899,495.
Application 17/899,495 is a continuation of application No. 17/223,910, filed on Apr. 6, 2021, granted, now 11,463,112.
Prior Publication US 2022/0416815 A1, Dec. 29, 2022
Int. Cl. H03M 13/37 (2006.01); G06F 11/10 (2006.01)
CPC H03M 13/3753 (2013.01) [G06F 11/1076 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method comprising:
receiving a codeword stored in a memory device;
identifying one or more bits in the codeword that are vulnerable to false flips by determining connections between the one or more bits and parity checks to identify trapping sets, stopping sets, or decoding cycles;
determining a bit flipping order for a bit flipping decoder using the one or more bits in the codeword identified as vulnerable to false flips; and
error correcting the codeword for one or more iterations by traversing the codeword according to the determined bit flipping order.