CPC H03L 7/0991 (2013.01) [G05B 13/042 (2013.01); H03L 1/00 (2013.01); H03L 1/02 (2013.01); H03L 7/093 (2013.01); H03L 2207/50 (2013.01)] | 20 Claims |
1. A tracking system for a digital Phase Locked Loop (PLL), the tracking system comprising:
a PLL model configured to emulate an actual internal PLL signal, wherein the emulation is based on another internal PLL signal received from the digital PLL and on an estimated analog PLL parameter of the PLL model,
wherein the digital PLL comprises a digital filter coupled between a phase difference digitizer and a digitally controlled oscillator (DCO), and the digital filter is configured to filter only a phase difference received from the phase difference digitizer; and
a tracker configured to compare the emulated internal PLL signal with the actual internal PLL signal, and to update the estimated analog PLL parameter according to a minimization algorithm that minimizes a result of the comparison.
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