US 11,705,906 B1
Majority logic gate having ferroelectric input capacitors and a pulsing scheme coupled to a conditioning logic
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Robert Menezes, Portland, OR (US); Ramamoorthy Ramesh, Moraga, CA (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on May 21, 2021, as Appl. No. 17/327,660.
Application 17/327,660 is a continuation of application No. 17/327,648, filed on May 21, 2021, granted, now 11,374,575.
Int. Cl. H03K 19/23 (2006.01); H01L 49/02 (2006.01)
CPC H03K 19/23 (2013.01) [H01L 28/55 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first capacitor having a first terminal and a second terminal, wherein the first terminal is to receive a first input, and wherein the second terminal of the first capacitor is coupled to a node;
a second capacitor having a third terminal and a fourth terminal, wherein the third terminal is to receive a second input, and wherein the fourth terminal of the second capacitor is coupled to the node;
a third capacitor having a fifth terminal and a sixth terminal, wherein the fifth terminal is to receive a third input, wherein the sixth terminal of the third capacitor is coupled to the node, and wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material; and
a reset mechanism coupled to the first capacitor, the second capacitor, the third capacitor, and the node, wherein the reset mechanism is to condition the first, second and third inputs in a reset phase separate from an evaluation phase, wherein the reset mechanism comprises a pass-gate, wherein the pass-gate is directly coupled to the node and an input node, wherein the input node is to provide a pulse signal, wherein the pass-gate is controllable by a reset signal, and wherein the pulse signal has a pulse width shorter than a duration of the reset phase.