| CPC H03K 5/135 (2013.01) [G11C 7/222 (2013.01); H03L 7/0814 (2013.01)] | 21 Claims |
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1. An apparatus comprising:
a delay stage including:
a clock enable circuit configured to receive first and second clock signals having a first frequency, configured to provide third and fourth clock signals having a second frequency that is a half of the first frequency;
a delay coupled to the clock enable circuit and configured to receive the third clock signal and to provide the third clock signal having an adjustable delay as an output clock signal;
a model delay circuit configured to receive the output clock signal and to provide the output clock signal having a model delay as a feedback signal; and
a measurement initialization circuit comprising:
a stop control circuit configured to provide a first stop signal to stop a measurement initialization responsive to the third and fourth clock signals and further responsive to the feedback signal, the stop control circuit comprising:
a plurality of synchronizers configured to receive the third and fourth clock signals, and complementary clock signals of the third and fourth clock signals respectively, and further configured to provide a plurality of second stop signals,
wherein the stop control circuit is configured to provide the first stop signal responsive to the plurality of second stop signals.
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