US 11,705,514 B2
MOS transistor structure with hump-free effect
Cheng Hua Lin, Hsinchu (TW); and Yan-Liang Ji, Hsinchu (TW)
Assigned to MediaTek Inc., Hsin-Chu (TW)
Filed by MediaTek Inc., Hsin-Chu (TW)
Filed on Apr. 26, 2016, as Appl. No. 15/138,683.
Claims priority of provisional application 62/198,323, filed on Jul. 29, 2015.
Prior Publication US 2017/0033214 A1, Feb. 2, 2017
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01)
CPC H01L 29/7816 (2013.01) [H01L 29/0653 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/0869 (2013.01); H01L 29/0886 (2013.01); H01L 29/1095 (2013.01); H01L 29/78 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A MOS transistor for power integrated circuits (ICs), comprising:
a semiconductor substrate having an active area, wherein the active area has a first edge and a second edge opposite thereto;
a gate layer disposed on the active area of the semiconductor substrate and having a first edge and a second edge opposite thereto, extending across the first and second edges of the active area;
first and second heavily doped regions of a first conductivity type in the active area at opposite sides of the gate layer and between the first and second edges of the active area; and
first and second heavily doped regions of a second conductivity type in the active area directly physically contacting the first and second heavily doped regions of the first conductivity type respectively, wherein
the first and second heavily doped regions of the second conductivity type have respective edges, and
the edges of the first and second heavily doped regions of the second conductivity type are coplanar with the first and second edges of the gate layer respectively.