US 11,705,506 B2
Lateral trench transistor device
Andreas Peter Meiser, Sauerlach (DE); and Till Schloesser, Munich (DE)
Assigned to Infineon Technologies Dresden GmbH & Co. KG, Dresden (DE)
Filed by Infineon Technologies Dresden GmbH & Co. KG, Dresden (DE)
Filed on Apr. 13, 2021, as Appl. No. 17/228,928.
Application 17/228,928 is a continuation of application No. 16/657,697, filed on Oct. 18, 2019, granted, now 11,018,244.
Claims priority of provisional application 62/748,070, filed on Oct. 19, 2018.
Prior Publication US 2021/0234023 A1, Jul. 29, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 21/225 (2006.01); H01L 21/768 (2006.01)
CPC H01L 29/66704 (2013.01) [H01L 21/225 (2013.01); H01L 21/76877 (2013.01); H01L 29/66696 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
epitaxially growing a semiconductor layer, the semiconductor layer including a drift zone of a first conductivity;
forming a trench in a first side of the semiconductor layer;
forming a drain region of the first conductivity type in the first side of the semiconductor layer and laterally adjoining the drift zone;
forming a body region of a second conductivity type opposite the first conductivity type and laterally adjoining the drift zone at a side of the drift zone opposite the drain region; and
forming source regions of the first conductivity type and body contact regions of the second conductivity type in a sidewall of the trench and arranged in an alternating manner along a length of the trench, using a dopant diffusion process which includes diffusing dopants of both conductivity types from oppositely-doped dopant source layers which are in contact with different regions of the sidewall.