US 11,705,485 B2
LDMOS transistors with breakdown voltage clamps
Vijay Parthasarathy, Sunnyvale, CA (US); Vipindas Pala, San Jose, CA (US); and Marco A. Zuniga, Berkeley, CA (US)
Assigned to Maxim Integrated Products, Inc., San Jose, CA (US)
Filed by Maxim Integrated Products, Inc., San Jose, CA (US)
Filed on Dec. 6, 2021, as Appl. No. 17/543,279.
Application 17/543,279 is a division of application No. 16/279,335, filed on Feb. 19, 2019, granted, now 11,195,909.
Claims priority of provisional application 62/632,726, filed on Feb. 20, 2018.
Prior Publication US 2022/0093730 A1, Mar. 24, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/78 (2006.01); H02M 3/158 (2006.01)
CPC H01L 29/0634 (2013.01) [H01L 29/0653 (2013.01); H01L 29/1095 (2013.01); H01L 29/404 (2013.01); H01L 29/7816 (2013.01); H01L 29/7819 (2013.01); H02M 3/158 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp, comprising:
a drain n+ region;
a source n+ region;
a gate;
an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction;
a p-type reduced surface field (PRSF) layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction;
a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction, the drain n+ region being disposed over the PBL in the thickness direction; and
an n-type drift (NDRFT) region disposed over the PRSF layer and adjacent to the NRSF layer in the lateral direction, wherein the drain n+ region is disposed in the NDRFT region.