CPC H01L 27/14687 (2013.01) [H01L 27/1463 (2013.01); H01L 27/14603 (2013.01); H01L 27/14632 (2013.01); H01L 27/14689 (2013.01)] | 17 Claims |
1. A method of forming a target shallow trench isolation (STI) structure in a semiconductor substrate, comprising:
etching a trench having a bottom and sidewalls in the semiconductor substrate, said trench having a depth (D) deeper than a target depth (TD) of the target STI structure and a width (W) wider than a critical dimension (CD) of the target STI structure;
reducing the depth and width of the trench by epitaxially growing a layer of semiconductor material in the trench until the depth equals the target depth and the width equals the critical dimension, wherein the semiconductor substrate and the layer of semiconductor material are formed of the same material;
depositing a dielectric material on the layer of semiconductor material in the trench and on the semiconductor substrate;
removing a portion of the dielectric material to form an oxide cap having a width greater than the CD and a height h above a substrate surface of the semiconductor substrate; and
forming a gate electrode of a transistor on at least a part of the oxide cap and the semiconductor substrate.
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