US 11,705,448 B2
Monolithic multi-I region diode limiters
James Joseph Brogle, Merrimac, MA (US); Joseph Gerard Bukowski, Derry, NH (US); Margaret Mary Barter, Lowell, MA (US); and Timothy Edward Boles, Tyngsboro, MA (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Jul. 13, 2021, as Appl. No. 17/374,314.
Application 17/374,314 is a division of application No. 16/788,853, filed on Feb. 12, 2020, granted, now 11,127,737.
Claims priority of provisional application 62/804,500, filed on Feb. 12, 2019.
Prior Publication US 2021/0343706 A1, Nov. 4, 2021
Int. Cl. H01L 27/06 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 23/66 (2006.01); H01L 29/868 (2006.01); H01L 27/08 (2006.01); H01L 21/822 (2006.01); H01L 29/66 (2006.01)
CPC H01L 27/0676 (2013.01) [H01L 21/2253 (2013.01); H01L 21/2254 (2013.01); H01L 21/26513 (2013.01); H01L 23/66 (2013.01); H01L 27/0814 (2013.01); H01L 29/868 (2013.01); H01L 21/822 (2013.01); H01L 29/6609 (2013.01); H01L 2223/6627 (2013.01); H01L 2223/6666 (2013.01); H01L 2223/6683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacture of a monolithic diode limiter semiconductor structure, comprising:
providing an N-type semiconductor substrate;
providing an intrinsic layer on the N-type semiconductor substrate;
implanting a first P-type region to a first depth into the intrinsic layer to form a first PIN diode comprising a first effective intrinsic region of a first thickness;
implanting a second P-type region to a second depth into the intrinsic layer to form a second PIN diode comprising a second effective intrinsic region of a second thickness; and
forming at least one blocking capacitor and at least one inductor over the intrinsic layer.