US 11,705,444 B2
Semiconductor memory system
Hayato Masubuchi, Kanagawa (JP); Naoki Kimura, Kanagawa (JP); Manabu Matsumoto, Kanagawa (JP); and Toyota Morimoto, Kanagawa (JP)
Assigned to KIOXIA CORPORATION, Minato-ku (JP)
Filed by KIOXIA CORPORATION, Minato-ku (JP)
Filed on Jun. 9, 2021, as Appl. No. 17/342,748.
Application 17/342,748 is a continuation of application No. 16/800,398, filed on Feb. 25, 2020, granted, now 11,063,031.
Application 16/800,398 is a continuation of application No. 16/502,288, filed on Jul. 3, 2019, granted, now 10,607,979, issued on Mar. 31, 2020.
Application 16/502,288 is a continuation of application No. 15/822,039, filed on Nov. 24, 2017, granted, now 10,388,640, issued on Aug. 20, 2019.
Application 15/822,039 is a continuation of application No. 15/378,947, filed on Dec. 14, 2016, granted, now 9,859,264, issued on Jan. 2, 2018.
Application 15/378,947 is a continuation of application No. 15/254,825, filed on Sep. 1, 2016, granted, now 9,754,632, issued on Sep. 5, 2017.
Application 15/254,825 is a continuation of application No. 14/511,676, filed on Oct. 10, 2014, granted, now 9,437,533, issued on Sep. 6, 2016.
Application 14/511,676 is a continuation of application No. 14/324,683, filed on Jul. 7, 2014, granted, now 9,312,215, issued on Apr. 12, 2016.
Application 14/324,683 is a continuation of application No. 13/418,619, filed on Mar. 13, 2012, granted, now 8,873,265, issued on Oct. 28, 2014.
Claims priority of application No. 2011-058140 (JP), filed on Mar. 16, 2011.
Prior Publication US 2021/0296300 A1, Sep. 23, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/02 (2006.01); H01L 25/18 (2023.01); H05K 1/02 (2006.01); H05K 3/30 (2006.01); H10B 69/00 (2023.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H05K 1/18 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/18 (2013.01) [G11C 5/02 (2013.01); H01L 23/3142 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5286 (2013.01); H01L 23/552 (2013.01); H01L 23/562 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H05K 1/0225 (2013.01); H05K 1/0271 (2013.01); H05K 1/0298 (2013.01); H05K 1/181 (2013.01); H05K 3/305 (2013.01); H10B 69/00 (2023.02); H01L 23/3121 (2013.01); H01L 2924/0002 (2013.01); H05K 2201/09136 (2013.01); H05K 2201/09681 (2013.01); H05K 2201/10159 (2013.01); Y02P 70/50 (2015.11)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate; and
a plurality of nonvolatile semiconductor memories on the substrate,
wherein the substrate includes:
a first metal layer having a first pattern density, the first metal layer being electrically connected to the nonvolatile semiconductor memories and being located on a first side of the substrate;
a second metal layer having a second pattern density, the second metal layer being located on a second side of the substrate;
a plurality of third metal layers disposed between the first and second metal layers and having respective third pattern densities; and
insulating layers provided between the first metal layer and a first one of the third metal layers adjacent to the first metal layer, between the second metal layer and a second one of the third metal layers adjacent to the second metal layer, and between adjacent ones of the third metal layers, wherein
a first group of metal layers includes n metal layers including the first metal layer and (n−1) adjacent third metal layers, a second group of n metal layers includes the second metal layer and (n−1) adjacent third metal layers different from the (n−1) third metal layers in the first group, a first density obtained from the first and third pattern densities of the first group of metal layers is substantially equal to a second density obtained from the second and third pattern densities of the second group of metal layers, and
at least one of the first and third pattern densities of the first group of metal layers and the second and third pattern densities of the second group of metal layers is 80% or greater.