US 11,705,436 B2
Semiconductor device and method for manufacturing the same
Takeori Maeda, Mie (JP); Yuusuke Takano, Mie (JP); and Soichi Homma, Mie (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 22, 2022, as Appl. No. 17/701,328.
Application 17/701,328 is a division of application No. 17/007,849, filed on Aug. 31, 2020, granted, now 11,302,675.
Claims priority of application No. 2020-024545 (JP), filed on Feb. 17, 2020.
Prior Publication US 2022/0216184 A1, Jul. 7, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/306 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/30625 (2013.01); H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 21/78 (2013.01); H01L 25/50 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06575 (2013.01); H01L 2225/06582 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, the method comprising:
providing a first semiconductor substrate having a first surface and a second surface opposite to each other;
forming a first resin layer on the first surface;
dicing the first semiconductor substrate into a plurality of first semiconductor chips;
providing a second semiconductor substrate having a third surface and a fourth surface opposite to each other;
coupling a connection bump on the third surface to a second resin layer;
connecting the connection bump to a wiring substrate; and
covering the connection bump between a second semiconductor chip and the wiring substrate with the second resin layer, wherein the second resin layer is disposed at a lower portion of a side surface of the second semiconductor chip.
 
12. A method for manufacturing a semiconductor device, the method comprising:
providing a first semiconductor substrate having a first surface and a second surface opposite to each other;
forming a first resin layer on the first surface;
dicing the first semiconductor substrate into a plurality of first semiconductor chips;
providing a second semiconductor substrate having a third surface and a fourth surface opposite to each other;
coupling a spacer chip to the first resin layer;
coupling a connection bump on the third surface to a second resin layer;
connecting the connection bump to a wiring substrate; and
covering the connection bump between a second semiconductor chip and the wiring substrate with the second resin layer, wherein the second resin layer is disposed at a lower portion of a side surface of the second semiconductor chip.