US 11,705,417 B2
Backside metallization (BSM) on stacked die packages and external silicon at wafer level, singulated die level, or stacked dies level
Chandra Mohan Jha, Tempe, AZ (US); Prasad Ramanathan, Chandler, AZ (US); Xavier F. Brun, Chandler, AZ (US); Jimmin Yao, Chandler, AZ (US); and Mark Allen, Gilbert, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 8, 2019, as Appl. No. 16/596,338.
Prior Publication US 2021/0104484 A1, Apr. 8, 2021
Int. Cl. H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/373 (2006.01); H01L 23/31 (2006.01)
CPC H01L 24/14 (2013.01) [H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/3735 (2013.01); H01L 23/53209 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a plurality of first dies on a substrate;
an interface layer over the plurality of first dies;
a backside metallization (BSM) layer directly on the interface layer, wherein the BSM layer includes a first conductive layer, a second conductive layer, and a third conductive layer; and
a heat spreader over the BSM layer, wherein the first conductive layer of the BSM layer is directly coupled to the interface layer, and wherein the third conductive layer of the BSM layer is directly coupled to the heat spreader.