US 11,705,214 B2
Apparatuses and methods for self-test mode abort circuit
Yoshinori Fujiwara, Boise, ID (US)
Assigned to Micron Technologv. Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 30, 2020, as Appl. No. 16/835,051.
Prior Publication US 2021/0304835 A1, Sep. 30, 2021
Int. Cl. G11C 29/00 (2006.01); G11C 29/18 (2006.01); G11C 29/50 (2006.01)
CPC G11C 29/18 (2013.01) [G11C 29/50012 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a command/address (C/A) circuit configured to provide an internal command signal and an address during a native operation mode and a self-test enable signal at an active level during a self-test mode;
a clock circuit configured to provide a self-test clock signal responsive to the self-test enable signal at an active level provided by the C/A circuit;
a self-test circuit configured to perform testing operations on a memory array responsive to the self-test enable signal at an active level provided by the C/A circuit and based on address information and a test sequence for the testing operations provided by a self-test sequencer; and
an abort circuit configured to:
change a count value responsive to the self-test clock signals; and
provide an abort signal when the count value matches or exceeds a threshold, the threshold longer than an expected length of the testing operations, wherein
the C/A circuit is further configured to stop providing the self-test enable signal at the active level responsive to the abort signal, and
the abort circuit includes a counter configured to change the count value responsive to each rising edge of the self-test clock signal.