CPC G11C 13/0069 (2013.01) [G11C 13/0004 (2013.01); G11C 2013/0092 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a memory having a plurality of memory cells; and
circuitry configured to program a memory cell of the memory by:
applying a first current pulse or a second current pulse to the memory cell, wherein the first current pulse and the second current pulse have different amplitudes or different durations; and
applying a third current pulse and a fourth current pulse to the memory cell.
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