US 11,705,194 B2
Systems and techniques for accessing multiple memory cells concurrently
Federico Pio, Brugherio (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 29, 2022, as Appl. No. 17/733,683.
Application 17/733,683 is a division of application No. 16/712,682, filed on Dec. 12, 2019, granted, now 11,335,402.
Claims priority of provisional application 62/782,015, filed on Dec. 19, 2018.
Prior Publication US 2022/0336013 A1, Oct. 20, 2022
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/003 (2013.01) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0061 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0045 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
identifying a first memory cell of a memory tile to program using a write operation;
identifying a second memory cell of the memory tile to access using a write operation or a read operation;
determining that accessing the second memory cell concurrently with programming the first memory cell is permitted on the memory tile during an access operation duration;
programming the first memory cell of the memory tile during the access operation duration; and
accessing the second memory cell of the memory tile concurrently with programming the first memory cell during the access operation duration based at least in part on determining that accessing the second memory cell concurrently with programming the first memory cell is permitted.