US 11,705,192 B2
Managing read level voltage offsets for low threshold voltage offset bin placements
Kishore Kumar Muchherla, Fremont, CA (US); Mustafa N. Kaynak, San Diego, CA (US); Michael Sheperek, Longmont, CO (US); and Shane Nowell, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 16, 2020, as Appl. No. 17/124,144.
Prior Publication US 2022/0189545 A1, Jun. 16, 2022
Int. Cl. G11C 16/26 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01)
CPC G11C 11/5642 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
creating a block family associated with a memory device;
associating the block family with a threshold voltage offset bin;
determining a set of read level voltage offsets such that, when applied to a base read level threshold voltage associated with the block family, result in a suboptimal error rate not exceeding a maximum allowable error rate, wherein the suboptimal error rate exceeds a minimum error rate for the block family; and
associating the set of read level voltage offsets with the threshold voltage offset bin.