US 11,705,188 B2
Output buffer circuit with metal option
Toshiaki Tsukihashi, Tama (JP); Kenichi Watanabe, Hachioji (JP); Kazuyuki Morishige, Sagamihara (JP); Moeha Shibuya, Sagamihara (JP); and Kumiko Ishii, Machida (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Nov. 17, 2021, as Appl. No. 17/529,101.
Application 17/529,101 is a continuation of application No. 16/800,899, filed on Feb. 25, 2020, granted, now 11,183,232.
Prior Publication US 2022/0076736 A1, Mar. 10, 2022
Int. Cl. G11C 11/4093 (2006.01); H10B 12/00 (2023.01)
CPC G11C 11/4093 (2013.01) [H10B 12/50 (2023.02)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a main driver comprising a plurality of transistors including a first transistor and a second transistor connected in parallel;
wherein the first transistor comprises a first wiring pattern and a second wiring pattern and the second transistor comprises a third wiring pattern and a fourth wiring pattern,
wherein first and second wiring patterns of the first transistor have a greater width in a first direction than the third and fourth wiring patterns of the second transistor,
wherein gate electrodes of the plurality of transistors are configured to connect to a ground potential or a first enable signal based on a wiring of a respective metal option, and
wherein the first transistor of the plurality of transistors is configured to receive the first enable signal and the second transistor of the plurality of transistors is configured to receive the ground potential.