US 11,705,186 B2
Storage and offset memory cells
Scott J. Derner, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Oct. 8, 2021, as Appl. No. 17/497,382.
Application 17/497,382 is a continuation of application No. 16/543,315, filed on Aug. 16, 2019, granted, now 11,145,358.
Claims priority of provisional application 62/725,889, filed on Aug. 31, 2018.
Prior Publication US 2022/0028447 A1, Jan. 27, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/12 (2006.01); G11C 11/4091 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01); G11C 7/06 (2006.01); G11C 8/08 (2006.01); G11C 11/4099 (2006.01); G11C 7/14 (2006.01)
CPC G11C 11/4091 (2013.01) [G11C 7/065 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01); G11C 7/14 (2013.01); G11C 11/4099 (2013.01)] 15 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of sense amplifiers, wherein each sense amplifier is coupled to a respective plurality of storage memory cells via a respective first digit line and a respective plurality of offset memory cells via a respective second digit line; and
a respective plurality of access devices coupled to the respective plurality of offset memory cells and the respective second digit line,
wherein respective voltages held capacitively by the plurality of storage memory cells correspond to data values, wherein respective voltages held capacitively by the plurality of offset memory cells do not correspond to data values, and wherein the plurality of offset memory cells have a cumulative capacitance that is approximately equal to a capacitance of the first digit line.