US 11,705,185 B2
Apparatus for differential memory cells
Daniele Vimercati, El Dorado Hills, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 29, 2021, as Appl. No. 17/362,280.
Prior Publication US 2022/0415381 A1, Dec. 29, 2022
Int. Cl. G11C 7/00 (2006.01); G11C 11/4091 (2006.01); G11C 11/408 (2006.01); G05F 3/26 (2006.01); G11C 5/06 (2006.01); G11C 11/4074 (2006.01)
CPC G11C 11/4091 (2013.01) [G05F 3/262 (2013.01); G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a pair of memory cells comprising a first memory cell and a second memory cell;
a word line coupled with the pair of memory cells;
a plate line coupled with the pair of memory cells;
a first digit line coupled with the first memory cell and a sense amplifier;
a second digit line coupled with the second memory cell and the sense amplifier;
a select line configured to couple the first digit line and the second digit line with the sense amplifier;
a pair of transistors configured to equalize voltages between digit lines and plate lines for unselected memory cells, the pair of transistors comprising a first transistor coupled with the plate line and the first digit line and a second transistor coupled with the plate line and the second digit line; and
a second select line coupled with the first transistor and the second transistor and configured to deactivate the first transistor and the second transistor to isolate the plate line from the first digit line and the second digit line.