CPC G11C 5/147 (2013.01) [G05F 3/24 (2013.01); G11C 16/30 (2013.01)] | 17 Claims |
1. A system, comprising:
a memory component; and
a processing device, operatively coupled to the memory component, to reduce a supply voltage sensitivity of an output current of a bias current generator circuit provided to the memory component, wherein the bias current generator circuit includes:
a plurality of transistors; and
a plurality of resistors coupled to the plurality of transistors, wherein:
a first one of the plurality of resistors is directly coupled to a source/drain region of a first one of the plurality of transistors and a source/drain region of a second one of the plurality of transistors;
a second one of the plurality of resistors is directly coupled to a source/drain region of a third one of the plurality of transistors and gates of both the second one of the plurality of transistors and a fourth one of the plurality of transistors; and
the first and third one of the plurality of transistors are directly coupled to ground.
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