US 11,705,164 B2
Bias current generator circuitry
Ming-ta Hsieh, Woodbury, MN (US); and Taylor Loftsgaarden, Eden Prairie, MN (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 6, 2022, as Appl. No. 17/833,535.
Application 17/833,535 is a continuation of application No. 16/838,205, filed on Apr. 2, 2020, granted, now 11,355,164.
Prior Publication US 2022/0301601 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G05F 3/24 (2006.01); G11C 5/14 (2006.01); G11C 16/30 (2006.01)
CPC G11C 5/147 (2013.01) [G05F 3/24 (2013.01); G11C 16/30 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory component; and
a processing device, operatively coupled to the memory component, to reduce a supply voltage sensitivity of an output current of a bias current generator circuit provided to the memory component, wherein the bias current generator circuit includes:
a plurality of transistors; and
a plurality of resistors coupled to the plurality of transistors, wherein:
a first one of the plurality of resistors is directly coupled to a source/drain region of a first one of the plurality of transistors and a source/drain region of a second one of the plurality of transistors;
a second one of the plurality of resistors is directly coupled to a source/drain region of a third one of the plurality of transistors and gates of both the second one of the plurality of transistors and a fourth one of the plurality of transistors; and
the first and third one of the plurality of transistors are directly coupled to ground.