US 11,705,085 B2
Gate driving circuit and display panel
Rongcheng Liu, Beijing (CN); Zhengwei Al, Beijing (CN); and Wenjun Gong, Beijing (CN)
Assigned to WUHAN BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Hubei (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/781,177
Filed by WUHAN BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan (Hubei) (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 9, 2021, PCT No. PCT/CN2021/099152
§ 371(c)(1), (2) Date May 31, 2022,
PCT Pub. No. WO2022/017041, PCT Pub. Date Jan. 27, 2022.
Claims priority of application No. 202010723520.0 (CN), filed on Jul. 24, 2020.
Prior Publication US 2023/0005445 A1, Jan. 5, 2023
Int. Cl. G09G 3/12 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01)
CPC G09G 3/3674 (2013.01) [G11C 19/28 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/06 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A gate driving circuit, comprising a plurality of shift register units as cascaded, wherein the plurality of shift register units as cascaded comprise:
a first shift register unit comprising a first clock signal terminal,
an (n+1)-th shift register unit comprising an (n+1)-th clock signal terminal,
a second shift register unit comprising a second clock signal terminal, and
an (n+2)-th shift register unit comprising an (n+2)-th clock signal terminal;
the gate driving circuit further comprises a first clock signal line connected to the first clock signal terminal and the (n+1)-th clock signal terminal, and a second clock signal line connected to the second clock signal terminal and the (n+2)-th clock signal terminal; and
the first clock signal line and the second clock signal line are arranged spaced apart, an input terminal of the first clock signal line is connected to one terminal of a first resistor, an input terminal of the second clock signal line is connected to one terminal of a second resistor, a resistance value of the second resistor is larger than a resistance value of the first resistor, and n is a positive integer greater than or equal to 2, n is a total number of clock signal lines.