CPC G09G 3/2096 (2013.01) [G09G 2300/0857 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] | 20 Claims |
9. A power management integrated circuit comprising:
a D flip-flop circuit configured to receive, through a first input port, an on-clock signal generated by a timing controller, to receive, through a second input port, a start clock signal generated by the timing controller, and to perform a logic operation thereon;
a first AND gate circuit connected to a first output port of the D flip-flop circuit and configured to output a gate start signal; and
a second AND gate circuit connected to a second output port of the D flip-flop circuit and configured to output a gate reset signal,
wherein the D flip-flop circuit filters and outputs a pulse of an input signal through an inverter and four AND gate circuits disposed therein, and
wherein the second AND gate circuit is connected to an output port of the inverter, the third AND gate circuit is connected to an output port of the first AND gate circuit and an output port of the fourth AND gate circuit, and the fourth AND gate circuit is connected to an output port of the second AND gate circuit and an output port of the third AND gate circuit.
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